1. Field of the Invention
The present invention generally relates to a fabrication method for a semiconductor memory. More particularly, the present invention relates to a fabrication method for a non-volatile memory.
2. Description of Related Art
Upon various non-volatile memories, electronic erasing programming read only memory (EEPROM), which can provide the advantages of multiple data writing, reading, erasing and the data maintained even after the disconnection or the power supply, has been widely applied to the personal computers and electronic equipments.
The material for the floating gate and the control gate of the conventional erasable and programmable read only memory is normally doped polysilicon. In order to prevent an over erasing which may lead to misinterpretation of data, a select gate is set-up on the side walls of the control gate and the floating gate, and the substrate to form a split-gate structure.
Conventionally, a charge trapping layer is applied to replace the polysilicon floating gate, and the material for the charge trapping layer can be, for example, silicon nitride. Normally, there are two silicon oxide layers above and under the charge trapping layer to form the oxide-nitride-oxide (ONO) structure. This kind of device is normally known as a silicon/silicon oxide/silicon nitride/silicon oxide/silicon (SONOS) device. The split-gate SNONS device has already been disclosed, for example, in U.S. Pat. No. 5,930,631.
However, the above mentioned split-gate SONOS devices require a larger spilt-gate region and a bigger size of the memory cell in order to set up the spilt-gate structure; therefore, the size of the split-gate SONOS device is bigger than that of the electrical erasable and programmable read only memory with a stacked gate. Therefore, the level of integration can not be increased.
TA non-volatile memory has been disclosed in the Taiwan patent application no: 93125069. As shown in the FIG. 1, the non-volatile memory is comprised of a few memory cells 102 and 116 to form a memory cell array. The memory cell 102 and memory cell 116 are separated by the spacer 110. The memory cell 102 is formed with a bottom dielectric layer 104a, a charge trapping layer 104b, a top dielectric layer 104c (the composite dielectric layer 104 is comprised of a bottom dielectric 104a, a charge trapping layer 104b and a top dielectric layer 104c), a gate 106 and a mask 108, and the above mentioned components are stacked sequentially from the substrate 100. Memory cell 116 is located between two memory cells 102. In a similar manner, the memory cell 116 is stacked, in order form the substrate 100, a bottom dielectric layer 112a, a charge trapping layer 112b, a top dielectric layer 112c (the composite dielectric layer 112 is further comprised of a bottom dielectric layer 112a, a charge trapping layer 112b and a top dielectric layer 112c), and a gate 214. As there is no spacer between the memory cells, the level of integration for this non-volatile memory can be increased.
However, according to the fabrication method disclosed by the prior art, the composite dielectric layer 104 of the memory cell 102 and the composite dielectric layer 112 of the memory cell 116 are manufactured under different processes; therefore the fabrication is more complex. Besides, the memory cell is formed in between two memory cells. Therefore, the composite dielectric layer 112 of the memory cell 116 is formed on a non-planar surface. An inconsistency between the memory cell 102 and memory cell 116 may occur due to the non-uniform thickness of the composite dielectric layer 112 of the memory cell 116. The reliability of the memory cell 116 is compromised.